The present invention relates generally to semiconductor device processing techniques, and, more particularly, to a structure and method for reducing short channel effects and parasitic capacitances in field effect transistors (FETs).
In the manufacture of semiconductor devices, there is a constant drive to increase the operating speed of certain integrated circuit devices such as microprocessors, memory devices, and the like. This drive is fueled by consumer demand for computers and other electronic devices that operate at increasingly greater speeds. As a result of the demand for increased speed, there has been a continual reduction in the size of semiconductor devices, such as transistors. For example, in a device such as a field effect transistor (FET), device parameters such as channel length, junction depth, gate dielectric thickness, and operating voltage, to name a few, all continue to be scaled downward.
Generally speaking, the smaller the FET, the faster the transistor will operate. While the interdependence of circuit switching speed on the transistor parameters is complex, the switching speed is typically benchmarked using the CV/I figure of merit, where C is the circuit load capacitance, V is the operating voltage, and I is the transistor effective “on” current during a switching event. The smaller the CV/I factor, the faster the switching speed will be. Typically, smaller FETs exhibit reduced operating voltage, similar or larger effective switching current, and similar or reduced parasitic capacitance, and, consequently, an increased switching performance. Moreover, by reducing the size and/or scale of the components of a typical transistor, there is also an increase in the density and number of the transistors that may be produced on a given amount of wafer real estate, thus lowering the overall cost per transistor as well as the cost of integrated circuit devices incorporating such transistors.
Unfortunately, reducing the channel length of a transistor also increases “short channel” effects, as well as “edge effects” that are relatively unimportant in long channel transistors. One example of a short channel effect includes, among other aspects, an increased drain to source leakage current when the transistor is supposed to be in the “off” or non-conductive state, due to an enlarged drain-to-body and source-to-body junction depletion region relative to the shorter channel length. In addition, one of the edge effects that may also adversely influence transistor performance is the gate-to-source/drain capacitance. A part of this parasitic fringe capacitance can be effectively increased via transistor gain factor, and is known as Miller capacitance. In CMOS applications, the Miller capacitance is an amplification of a gate to drain capacitance.
The gate-to-source/drain capacitance typically includes several distinct components: direct overlap (Cdo), outer fringe (Cof), inner fringe (Cif), and gate-to-contact stud (Cstud). The first three components are often cumulatively referred to as overlap capacitance (Cov). Direct overlap capacitance exists primarily as a result of the gate electrode and gate dielectric that (almost invariably) overlaps with a conductive portion of the source/drain regions and/or the source/drain extension (SDE) regions (if present) of the FET. The outer fringe capacitance is typically a corner capacitance between more vertically oriented gate conductor wall and more horizontally oriented source/drain surface separated by dielectric spacers. The inner fringe capacitance is also a corner capacitance between more horizontally oriented gate electrode interface adjacent to the gate dielectric and more vertically oriented source/drain junction adjacent to the transistor body. In the case of inner fringe capacitance, the conductive surfaces are separated by thin gate dielectric and depleted transistor body. The relative contribution of the overlap capacitance to the overall device capacitance increases as the gate length is scaled down. For example, Cov can account for as much as 50% of the overall capacitance when a MOSFET has a scaled gate length of about 30 nanometers.
Accordingly, it would be desirable to be able to fabricate an FET that maintains a low series resistance between the channel and the drain and between the channel and the source of the device, while at the same time retaining beneficially reduced short channel effects and minimizing the parasitic capacitances of the device including the Miller capacitance between drain and gate, the source-to-gate capacitance, and the junction capacitances formed between source/drain regions and transistor body, depending on the device application.